1. Field of the Invention
The present invention relates to a general-purpose semiconductor integrated circuit for realizing a variety of logic functions required in various applications by combining of a plurality of logic circuits expressing discrete logical operations. In the present invention, individual logic circuits are each constructed by combining pass-transistor logic circuits and a multiple-input logic gate. Complex logical operations can be efficiently expressed using the logic circuity disclosed herein, which can operate at a high speed. The present invention also relates to a method of forming the logic circuits used in such an integrated circuit, as well as a method of executing various logical operations.
The present invention furthermore relates to a base cell used to construct a semiconductor integrated circuit in the form of a gate array, and more particularly, to a programmable logic block for use in a field programmable gate array integrated circuit. The present invention likewise relates to a method of programming such a programmable logic block.
2. Description of the Related Art
It is known in the art to realize a semiconductor integrated circuit comprising a plurality of logic circuits expressing various logical operations on a semiconductor substrate. The resulting integrated circuit realizes functions required in electronic applications by combining logical operations expressed by the logic circuits. Semiconductor integrated circuits of this type are widely used in the industry.
An example of this type of semiconductor integrated circuit is a full-custom integrated circuit. In the full-custom integrated circuit, the types, the dimensions, and the layouts of basic elements such as MOS transistors or other switching devices constituting the logic circuits are determined in accordance with the logical operation to be realized by the logic circuit. Masks required to fabricate the integrated circuit are produced, and the integrated circuit is then fabricated using these masks.
Another type of semiconductor integrated circuit is a gate array, which is also widely used in the industry. In gate arrays, basic cells each including a predetermined number of switching devices, each having a predetermined structure with predetermined dimensions, are arranged in an array on a surface of a semiconductor substrate. Logical operations are expressed by properly setting the interconnections within each basic cell. The gate array integrated circuit can realize different functions by properly making interconnections among the basic cells.
A typical example of gate array integrated circuits is a mask programmable gate array. In a mask programmable gate array, a semiconductor substrate (master slice), on which basic cells having no interconnections are arranged in an array, is prepared first. Interconnections among switching devices within each basic cell and interconnections among basic cells are determined depending on the function required in a specific application. Masks required to form the determined interconnections are then produced. Using these masks, interconnections are formed on the master slice which has already been prepared, thereby fabricating an integrated circuit having the desired function.
The mask programmable gate array reduces turn around time, and thus the cost, required to design and produce integrated circuits having given desired functions. Thus, the mask programmable gate array provides users with an efficient means of realizing their own integrated circuits required by their specific applications.
In recent years, a field programmable gate array (FPGA), in which each basic cell includes programmable interconnections with programmable switches, has also been widely used. In the FPGA, a user can set programmable switches in each basic cell (often called a programmable logic block in the art of the FPGA) to either ON state or OFF state by programming, so that logic circuits required in an application are configured in the programmable logic blocks. The different programmable logic blocks are connected to each other via programmable interconnections among programmable logic blocks. Thus, the user can realize a desired integrated circuit by programming the programmable interconnections of the FPGA at the user's site. Pass transistors driven by data stored in an SRAM, EEPROM or similar devices, or anti-fuses are generally used as the switches.
It is also known in the art to employ a "pass-transistor logic circuit" to reduce the number of elements and improve operating speed (as for example U.S. Pat. No. 4,541,067). Pass-transistor logic circuits use pass transistors each comprising a switching device. Conduction between an input terminal and output terminal of the switching device is turned ON or OFF according to a potential at a control terminal. Each pass transistor is realized by connecting the switching devices so that whether a logic signal applied to the input terminal is transmitted to the output terminal can be determined with the conducting or nonconducting state of each switching device. In general, a plurality of pass transistors are connected in series and/or parallel to constitute a pass-transistor logic circuit for calculating a desired logical operation. As for the switching devices, MOS transistors, for example, may be used. In this case, the gate, source, and drain of each MOS transistor correspond to the control, input, and output terminals, respectively.
Use of such the pass transistor logic circuit allows a reduction in the number of required elements and an improvement in operating speed.
A specific example of a pass-transistor logic circuit is disclosed in U.S. Pat. No. 4,559,609, in which it has been demonstrated that a full adder can be realized using a pass-transistor logic circuit with a smaller number of transistors than required when the full adder is realized using only MOS transistor NOR gates. Although this patent discloses a technique of realizing a circuit for producing a C (carry) integral in the full adder, using six pass transistors and one triple-input NOR gate, the patent does not disclose a general technique to realize various logic circuits with a combination of pass transistors and a multiple-input logic gate, other than the circuit for producing a carry signal. In fact, in the above patent, the circuit to produce a carry signal is the only logic circuit that has been realized by a combination of pass transistors and a multiple-input logic gate. On the other hand, the circuit to produce an S (sum) signal is realized by using pass transistors and inverters without using a multiple-input logic gate.
K. Yano et al., have proposed three types of pass-transistor logic circuit cells Y1 to Y3 such as those shown in FIG. 1 in their paper entitled "Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs" (IEEE 1994 Custom Integrated Circuits Conference, p. 603). In these cells Y1 to Y3, pass-transistor logic circuits are constructed with a plurality of N channel MOS transistors M1 to M6, and an inverter I is connected to each pass transistor logic circuit. The cell Y1 is a single-stage pass-transistor logic circuit. The cell Y2 is a pass-transistor logic circuit in the form of a combination of a single-stage pass-transistor logic circuit and a dual-stage pass-transistor logic circuit. The cell Y3 is a full double-stage pass-transistor logic circuit. In these cells, each inverter I is constructed with two N channel MOS transistors M1 and M2 and three P channel MOS transistors M3 to M5, as shown in FIG. 2.
In FIG. 2 and other figures, T-shaped symbols are used to denote terminations connected to first power supply means for supplying a power supply potential. Interconnections terminated by inverted triangles are assumed here to be connected to second power supply means for supplying a reference potential. The ground potential is generally employed as the reference potential.
Other pass transistor logic circuits are also disclosed in the co-pending patent application Ser. No. 08/716,883.
It is also known in the art to use a pass transistor logic circuit to form a basic cell of a gate array. For example, a pass-transistor logic circuit which is constructed with three pairs of N channel MOS transistors to produce complementary output signals OUT and OUT is disclosed in a technical paper entitled "Pass Transistor Based Gate Array Architecture" (Y. Sasaki et al., 1995 Symposium on VLSI Circuit Digest of Technical Papers 16-1). The outputs of the pass transistor logic circuit are latched (or pulled up) by cascode-connected small-size P channel MOS transistors so as to prevent interference with a circuit in the succeeding stage. Furthermore, an inverter for driving the circuit in the succeeding stage is provided at the outputs of the pass-transistor logic circuit. The technical paper cited herein above also discloses a gate array using basic cells each including transistors which can construct two above-described pass-transistor logic circuits.
FIG. 1 of this technical paper is shown herein as FIG. 3. In this prior art, complementary input signals are applied to a pass-transistor tree constructed with N channel MOS transistors, and the results of the logical operation performed by the pass-transistor tree are output as OUT and OUT in a complementary form. The outputs OUT and OUT are connected to a latch consisting of two P channel MOS transistors.
As shown in FIG. 4 corresponding to FIG. 5 of the technical paper cited herein above, an SRAM (static random S access memory) cell can be formed using the above basic cells. In FIG. 4, the input and the output of an inverter constructed with a P channel MOS transistor P1 and an N channel MOS transistor N1 are connected to the output and the input of an inverter constructed with a P channel MOS transistor P2 and an N channel MOS transistor N3, respectively, so that a latch is formed. The latch is connected to a pair of bit lines via N channel MOS transistors N2 and N4, wherein the gate of each MOS transistors N2 and N4 is connected to a word line.
Further, some FPGAs employ pass transistors as basic elements of the programmable logic blocks.
For example, U.S. Pat. No. 5,367,208 discloses an FPGA including programmable logic blocks each having a structure shown in FIG. 5. An N channel MOS transistor M1 and a P channel MOS transistor M2 form a first pass-transistor (called a "pass gate"). Similarly, an N channel MOS transistor M3 and a P channel MOS transistor M4 form a second pass gate. Thus, the programmable logic block shown in FIG. 5 includes a single-stage pass-transistor logic circuit.
FIG. 6 shows a programmable logic block employed in an FPGA disclosed in U.S. Pat. No. 4,870,302. As shown, this programmable logic block comprises eight pass transistors, two inverters 21 and 22 and a complex gate including a dual-input OR gate 23, a dual-input AND gate 24, a triple-input AND gate 25, and a dual-input NOR gate 26. In this programmable logic block, the logic states of configuration control signals C0, C0, C1, C1, . . . , C5 are determined such that a desired logical operation is expressed by the logic block. These configuration control signals are applied to the control terminals of the respective pass transistors, so that the respective pass transistors are in either ON state or OFF state. When this logic block is actually operated as the logic circuit, the configuration signals C0 through C5 are maintained at the determined states. Input signals A and B are input to this logic circuit from, for example, a logic circuit realized using another programmable logic block at the preceding stage. The input signals A and B are input to corresponding input nodes of the complex gate either directly without being inverted or indirectly after being inverted by the inverter 21 or 22, depending on the states of the pass transistors. The complex gate performs a logical operation on the received signals, and provides the result via the output node.
For example, if the configuration control signals C0 and C1 are set to HIGH state, the pass transistors 29c and 29d are in ON states and thus the input signals A and B are directly input to the input nodes of the triple-input AND gates 25. Furthermore, if the configuration control signal C5 is also set to HIGH state, the result of logical AND operation between A and B is provided at the output of the AND gate 25. On the other hand, if C0 and C1 are set to HIGH state, the input signals A and B are input to the input nodes of the triple-input AND gate 25 after being inverted by the inverters 21 and 22, respectively. In this case, the result of logical AND operation of A and B is provided at the output of the triple-input AND gate 25. In the programmable logic block of this technique, as described above, each pass transistor simply serves to transmit an input logic signal to a complex gate either directly without being inverted or after being inverted, and a logical operation such as AND or OR on the input logic signals is effectively performed solely by a complex gate.